1. Field of the Invention
Example embodiments of the invention are directed to photomask configurations and methods utilizing such photomasks in fabricating semiconductor devices and, more particularly, to photomask configurations utilized in forming contact openings during the fabrication of semiconductor devices and methods of forming contact openings using such photomasks.
2. Description of the Related Art
As semiconductor devices have become more highly integrated, the critical process dimensions, for example, the spacing between adjacent conductive lines, are being reduced accordingly. The increased degree of integration has led to other changes in the fabrication process as well including, for example, delaying formation of capacitor structures until after formation of the bit lines in semiconductor memory devices such as DRAMs to provide additional surface area for capacitor formation. The semiconductor device fabrication process also typically includes the formation of contact plugs for establishing electrical connection between, for example, conductive regions provided in the semiconductor substrate and upper structures, for example, bit lines and/or capacitor electrodes.
FIG. 1A and FIG. 2A are plan views illustrating a conventional method for forming such contact plugs. FIG. 1B and FIG. 2B are cross-sectional views taken along a portion of the line B-B on FIG. 1A and FIG. 2A respectively, the illustrated portion generally corresponding to a single active region. As illustrated in FIGS. 1A and 1B, a plurality of elongated active regions 14 are formed in a semiconductor substrate 10 and aligned along their major axis to form a plurality of lines paralleling a first axis A. The active regions 14 are electrically isolated from adjacent active regions using an isolation layer 12. A plurality of gate lines 16 paralleling a second axis G are then formed over the active regions 14. The axes A and G are not perpendicular and accordingly intersect to form complementary pairs of acute and obtuse angles.
The gate lines 16 may have a stack structure including a gate insulator (not shown), a gate electrode 17, for example polysilicon, an additional low resistance conductor 18, such as a polycide or salicide, for improving the electrical conductivity of the gate electrode, and a capping pattern 19, typically formed from an insulating material, as a protecting layer. Insulating spacers 20 may also be formed on the sidewalls of the gate lines 16 and may have single or multilayer construction. An interlayer insulating layer 22 may also be provided over the gate lines 16 for controlling the depth of the subsequently formed contact plug and improving the associated photolithographic process.
Contact holes 24 are formed through the insulating materials to expose portions of the active regions 14 between the gate lines 16 and provide an opening for the formation of contact plugs that will be utilized for electrically connecting the active regions to, for example, a bit line or a lower electrode of a capacitor. The contact hole 24 is typically formed using a photomask having a plurality of generally circular transparent windows (hereinafter, referred to as a “hole pattern”). An interlayer insulating layer 22 may be utilized for improving the planarity of the substrate before patterning by deposing the interlayer insulating layer on the semiconductor substrate 10 to cover the gate lines 16. An upper portion of the interlayer insulating layer 22 may then be removed using a CMP, etchback or equivalent process to form a planarized surface. The amount of the interlayer insulating layer removed may result in an upper surface of the capping pattern 19 (if present) or the gate line 16 being exposed or may continue to completely encapsulate the gate lines 16.
A photoresist layer (not shown) is then formed on the surface of the planarized interlayer insulating layer 22 and exposed using a photomask having the hole pattern. The exposed photoresist is then developed to form a photoresist pattern exposing those regions of the semiconductor substrate in which contact holes will be formed. Using the photoresist pattern as an etch mask, portions of the remaining interlayer insulating layer 22 are removed to expose portions of the active regions 14. Depending on the particular configuration of the gate lines 16, the materials utilized, the etch processes and the critical spacings, the contact hole etch may also remove portions of the insulating spacer 20 (if present), the capping pattern 19 (if present) and/or the gate line 16.
As illustrated in FIGS. 2A and 2B, the photoresist pattern is then removed and a conductive material layer, for example, tungsten (W), is deposited on the semiconductor substrate to fill the contact holes 24. An upper portion of the conductive material layer is then removed to expose an upper surface of the interlayer insulating layer 22 and thereby separating those portions of the conductive material layer remaining in the contact holes and thereby forming contact plugs 26, 28. As illustrated in FIGS. 2A and 2B, the contact plugs include both a bit line contact plug 26, i.e., a plug that will subsequently be connected to a bit line, and lower electrode contact plugs 28, i.e., plugs that will subsequently be connected to the lower electrode of a capacitor.
As the distance between the gate lines 16 of a highly integrated semiconductor device is reduced, the exposed portions of the active regions 14, for example, a diagonal-shaped portion of the active region (hereinafter, referred to as “active region”) is also reduced. In order to form the contact hole 24 between the narrowly spaced gate lines 16, a photolithography process must be performed using a light source having a relatively short wavelength, for example, that provided by an ArF light source. In comparing equipment utilizing light sources that can provide the same wavelength, another consideration is the numerical aperture provided by exposure equipment with higher numerical apertures, for example, at least about 0.93, generally being utilized for patterning smaller critical dimensions. However, equipment having both light source capable of producing short wavelength light or providing a higher numerical aperture will tend to be much more expensive than conventional equipment and may also provide lower throughput, thereby further increasing the cost per exposure. Accordingly, the patterning improvements provided by such exposure equipment may be difficult to justify for high volume production requirements.
As the distance between the gate lines 16 is reduced, the likelihood and, if present, the severity of etch striation phenomenon within the contact hole 24 will tend to become more severe. In order to suppress this striation phenomenon, the method of fabricating the contact hole may be modified to include a polymer hard photomask and/or an additional hard photomask of silicon nitride formed on the surface of the interlayer insulating layer 22.